The present invention relates to a manufacturing technique of a semiconductor device and more particularly to a technique which is useful for the application to the manufacture of a semiconductor element having a metal silicide layer.
With the progress of high integration of a semiconductor device, a field effect transistor is miniaturized in accordance with the scaling law, however, there arises a problem that a high-speed operation cannot be obtained even if the field effect transistor is miniaturized because the resistance of a gate, source, and drain increases. Consequently, for example, for a field effect transistor having a gate length of 0.2 μm or less, a SALICIDE (Self Aligned Silicide) technique is under study, which reduces the resistance of a gate, source, and drain by forming a silicide layer with a low resistance, for example, such as a nickel silicide layer and cobalt silicide layer, over the surface of a conductive film constituting a gate and a semiconductor region constituting a source and drain by means of self-alignment.
For example, in Japanese patent laid-open No. 11-251591 (patent document 1), a technique is disclosed, which forms a silicide layer with a low resistance by, after forming a silicide compound rich in metal by carrying out first annealing of a metal film including Ni, Co. Mo, Ta, W, Cr, Pt, or Pd, removing unreacted metal film and by further carrying out second annealing of the silicide compound.
In Japanese patent laid-open No. 2007-184420 (patent document 2), a technique is described, which forms a silicide by, after forming a metastable Ni silicide by annealing a silicon substrate in which Ni is formed as a first sinter at temperatures not lower than 250° C. and not higher than 500° C., removing unreacted Ni and further annealing as a second sinter at temperatures higher than those of the first sinter to cause Ni and Si to react each other.
In Japanese patent laid-open No. 5-29343 (patent document 3), a technique is described, which forms a silicide film by, after forming a titanium silicide film by annealing Ti for a brief time in the atmosphere of N2 at 600° C., removing a titanium nitride layer and titanium layer and further injecting a silicon ion beam once or more, and then annealing in the atmosphere of N2 at about 800° C.
In Japanese patent laid-open No. 2007-142347 (patent document 4), a technique is described, which carries out a thermal treatment after sequentially depositing a nickel alloy film and a nickel film over a semiconductor substrate in a step of forming a nickel alloy silicide layer over at least one of a gate electrode and a source/drain region.
Patent Document 1
    Japanese patent laid-open No. 11-251591Patent Document 2    Japanese patent laid-open No. 2007-184420Patent Document 3    Japanese patent laid-open No. 5-29343Patent Document 4    Japanese patent laid-open No. 2007-142347
A nickel silicide layer in a mono metal silicide (NiSi) phase has a low resistance of 14 to 20 μO·cm, and can be formed by the SALICIDE technique at comparably low temperatures, for example, 400 to 600° C. Consequently, the formation of a shallow junction with a low resistance is made possible, and therefore, a nickel silicide layer is adopted recently for the source/drain of a field effect transistor required to be miniaturized.
For the formation of the nickel silicide layer in the NiSi phase, thermal treatment in two stages is used generally. First, in order to deposit a nickel film over a wafer to form the NiSi phase, a first thermal treatment is carried out. As conditions on the first thermal treatment, for example, a temperature of 410° C., a time of 30 seconds, and a temperature rise rate of 5° C./s can be enumerated.
For the first thermal treatment, for example, a lamp heating device 101 shown in FIG. 30 can be used. FIGS. 30(a), 30(b), and 30(c) are respectively a plan view of a general configuration of the lamp heating device, a section view of essential parts in a chamber, and a plan view of essential parts of a susceptor part.
As shown in FIG. 30(a), a wafer is accommodated in a FOUP 102 docked to the lamp heating device 101. The wafer taken out from the FOUP 102 is transferred to a load lock 103. In order to suppress outside air (mainly oxygen) from entering a processing chamber 105 mixedly, the interior of the load lock 103 is temporarily depressurized to 133.32 Pa or less and then its pressure is restored to the atmospheric pressure. After that, the wafer is transferred to one of the processing chambers 105 via a transfer chamber 104 etc. Before a first wafer is transferred to the processing chamber 105, the chamber 105 is heated and the oxygen remaining in the chamber 105 is thermally discharged. The wafer having been subjected to a predetermined thermal treatment is cooled down, returned to the transfer chamber 104, and then returned to the FOUP 102 via the load lock 103.
As shown in FIGS. 30(b) and 30(c), a wafer SW is heated from the side of a wafer surface SWs by infrared radiation of a halogen lamp 106 installed in the processing chamber 105. The outputs of the 409 halogen lamps 106 in the processing chamber 105 are controlled while the wafer temperature is being read from the side of a wafer rear surface SWr using pyrometers 107. The pyrometers 107 are arranged from the wafer center toward the periphery and read the temperature in the wafer plane and feed it back to the power of the halogen lamp 106 in the zone corresponding to the position of each pyrometer 107.
However, variations in temperature in the wafer plane are caused because (1) the number of halogen lamps 106 is large and therefore there is a difference in the amount of heat radiated from among the halogen lamps 106, (2) the heating in the wafer plane is not uniform due to a small difference in horizontally between the halogen lamp 106 and a susceptor (Edge Ring) 108 that holds the wafer SW, etc. It is possible to reduce the variations in temperature in the wafer plane by rotating the wafer SW to suppress the above-mentioned phenomenon. However, because the outermost periphery of the wafer SW comes into contact with the entire surface of the susceptor 108, the temperature of the wafer periphery is impeded from rising and in particular, until a temperature zone (about 280° C.) where control is possible is reached, the variations in temperature in the wafer plane are likely to be caused.
After the first thermal treatment, the unreacted nickel film is removed and a second thermal treatment for stabilizing the NiSi phase is further carried out. As the conditions on the second thermal treatment, for example, a temperature of 550° C., a time of 30 seconds, and a temperature rise rate of 3 to 10° C./s can be enumerated.
Table 6 shows an example of a process recipe of the second thermal treatment. In the second thermal treatment also, the lamp heating device 101 shown in FIG. 30 described above can be used. First, a small amount of heat (lamp power 5%) is given to the processing chamber 105 (Step No. 1) and a standby state is maintained until the concentration of oxygen in the processing chamber 105 becomes 5 ppm or less (Step No. 2). Then, the wafer SW is transferred to the processing chamber 105. Following this, the power to be input to the halogen lamp 106 is set to raise the temperature of the wafer SW at a low rate and the wafer SW is heated until a temperature zone (about 280° C.) is reached, where the temperature of the wafer can be read and the control of the wafer temperature becomes possible (Step No. 3). As described above, the wafer SW is heated by the infrared radiation of the halogen lamp 106, and therefore, the variations in temperature in the wafer plane are likely to be caused in a low-temperature range, such as a range of temperatures between room temperature and about 280° C. Consequently, a step (Step No. 4) is provided, in which the temperature is raised at a low rate in order to reduce the variations in temperature in the wafer plane in this temperature zone. Subsequently, the temperature of the wafer SW is kept at a constant temperature (300° C.) and after the variations in temperature in the wafer plane are controlled (Step No. 5), the temperature of the wafer SW is raised to a thermal treatment temperature (550° C.) (Steps No. 6, No. 7), and the second thermal treatment is carried out (Step No. 8). After the second thermal treatment is completed, the supply of power to the halogen lamp 106 is returned to that in the standby state and the temperature of the wafer SW is reduced (Step No. 9).
TABLE 6Step No.12345678StepPURGE02OLSORSTABRAMP UPRAMPSOAKNameCHECKUP2To NextTIME02 < 5 ppmTEMP > 280SETPTIMESETPSETPTIMEStepTHERETHERETHERETime20202051510530SettingCONST.VCONST.VRAMP VRAMPSTABRAMPRAMPCONST. TEMPTEMPTEMPTEMPTEMPTemp.5%——280-300300300-535535-550550Temp——0.1%/s5° C./s—20° C./s3° C./s—RampRateN21515151515151515He1.51.51.51.51.51.51.51.5Rot.—45240240240240240240
However, about the nickel silicide layer formed by the SALICIDE technique, there are various technical problems to be described below.
That is, it has been revealed that there are many defects on the surface of the nickel silicide layer in the NiSi phase formed by the thermal treatment in the two stages described above and variations in electrical characteristics are caused. This may result from aggregation of Ni and Si due to the application of an excessive amount of heat to the wafer in the second thermal treatment carried out to stabilize the NiSi phase. As described above using Table 6, in the second thermal treatment, after the wafer is heated until a temperature zone (about 280° C.) is reached, where the wafer temperature can be read and controlled, the period of time during which the temperature of the wafer SW is kept at a constant temperature (300° C.) is 20 to 30 seconds (Steps No. 4, No. 5) and further, the time required until the temperature is raised to the thermal treatment temperature is about 15 seconds (Steps No. 6, No. 7), and thus, an excessive amount of heat corresponding to the period of time of about 40 seconds is applied to the wafer SW besides the thermal treatment (Step No. 8). Further, before an insulating film is formed over the nickel silicide layer, the surface of the nickel silicide layer is subjected to the plasma cleaning process and the change in composition of NiSi due to the plasma cleaning process is one of the causes of the occurrence of defects. Since the plasma cleaning technique is disclosed in Japanese Patent Application No. 2007-259355 (filed on Oct. 3, 2007), duplicated parts are not repeated here as a general rule.
Because of such circumstances, the present inventors have studied a nickel silicide layer to which platinum is added (hereinafter, referred to simply as platinum-added nickel silicide layer) in order to reduce the defects on the surface of the above-mentioned nickel silicide layer. However, it has been revealed that, when forming a platinum-added nickel silicide layer, the temperature of the first thermal treatment of the thermal treatment in two stages is the temperature zone (about 280° C.) where the wafer temperature can be read and controlled and it is difficult to stably carry out the first thermal treatment to form the platinum-added nickel silicide layer in the mono metal silicide (PtNiSi) phase. Further, in the first thermal treatment, because the wafer SW is heated by the infrared radiation of the halogen lamp 106, it takes time to raise the temperature to the thermal treatment temperature (about 280° C.) and therefore an excessive amount of heat is applied to the wafer. As a result, the platinum-added nickel silicide layer after the first thermal treatment includes not only the PtNiSi phase but also a plurality of phases other than the PtNiSi phase, resulting in variations in resistance values of the platinum-added nickel silicide layer. In addition, because the lower limit temperature above which the wafer temperature can be controlled is adopted, it is not possible to increase the temperature rise rate. Furthermore, it has been revealed that the reduction in defects on the surface of the platinum-added nickel silicide layer formed by the thermal treatment in two stages is small and a remarkable effect of the addition of platinum cannot be obtained.